Conventionally, a liquid crystal display device has been developed which has a standby mode for driving the liquid crystal display device with low power consumption. In the standby mode, when a display is temporarily unnecessary, the liquid crystal display device enters into a standby state in which the display is turned OFF, and then, once the display is required, the standby state is cancelled and the liquid crystal display device again carries out a normal display.
In such a standby mode, while the display is not required, circuits (such as a data generator, a timing generating circuit, and a control signal generating circuit) in a driver are controlled to be in a resting state. This prevents the driver from consuming electric power.
However, in a case where a current-alternating signal is also stopped while a liquid crystal driving voltage is being applied, the liquid crystal is driven by a direct current. This causes a significant decrease in reliability of liquid crystal.
As a measure for dealing with such a phenomenon, Patent Literature 1 discloses a circuit which carries out an AC driving of liquid crystal even during a standby mode.
FIG. 9 illustrates a configuration of a liquid crystal display control circuit disclosed in Patent Literature 1.
A timing generating circuit 102 generates a basic timing based on a CK which is a basic clock input. A control signal generating circuit 103 generates signals, which are required for controlling a liquid crystal display (LCD), such as YD (scanning start pulse for Y driver), WF (current-alternating signal), LP (latching pulse for X driver and shift clock for Y driver), and XSCL (shift clock for X driver). A selector 105 supplies an A-input to Y when a select input S is at an “H” level, and supplies a B-input to the Y when the select input S is at an “L” level.
An oscillating circuit 107 generates a clock oscillating at a low frequency. A frequency dividing circuit 104 further divides the frequency of the clock generated by the oscillating circuit 107.
When entering into the standby mode, STNBY becomes the “L” level, and an output of an AND gate 106 is fixed at the “L” level. This causes the timing generating circuit 102, the control signal generating circuit 103, and a data generator 101 to be in the resting state.
On the other hand, in a case where a select input S is at the “L” level, the B-input is selected, and a signal 113 is supplied to the WF and the LP. That is, in the standby mode, the low frequency clock generated by the oscillating circuit 107 is supplied, as the signal 113, to the selector 105 via the frequency dividing circuit 104. In response to the signal 113 thus supplied, the selector 105 outputs (i) an LP for deselecting all Y drivers and (ii) a WF required for driving the liquid crystal by alternating currents.
As such, in the standby mode, (i) the timing generating circuit 102 and the control signal generating circuit 103 are controlled to be in the resting state and (ii) the WF and the LP can be supplied to the LCD by use of the low frequency clock. This allows (i) a reduction in power consumption and (ii) prevention of the LCD from being driven by a direct current.
In recent years, a display device has been known in which memory circuits (hereinafter, referred to as “pixel memory”) are provided for respective pixels so that respective pieces of image data are stored in the pixel memories. This allows a still image to be displayed without continuously supplying image data from outside, and therefore the still image can be displayed with low power consumption.
For example, Patent Literature 2 discloses a display device including such a pixel memory.
FIG. 10 illustrates a configuration of a display device of Patent Literature 2, which includes a pixel memory.
The display device includes an X address scanning line driver 218, a digital data driver 219, and an analog data driver 220. Further, the display device is switchable between a digital data image display mode and an analog data image display mode.
In the digital data image display mode, an X address signal line 204-n (n is a natural number) connected with a pixel, into which image data is to be written, is selected, and a digital data signal, which has been supplied to a first switch element 208 of the pixel from a corresponding first display control line 1-n, is written into a digital memory element 250 made up of an NAND circuit 251 and a clocked inverter element 253. At that time, the digital memory element 250 has been made active by a signal supplied via a display mode control line 215.
The digital memory element 250 has (i) an input which is connected with a second switch element 209 and (ii) an output connected with a third switch element 210. With the configuration, any one of the second switch element 209 and the third switch element 210 becomes conductive depending on High/Low of the digital data signal. A white display reference voltage is supplied to one of a second display control line 202-n and a third display control line 203, and a black display reference voltage is supplied to the other. A white voltage or a black voltage, which is determined by a conductive one of the second switch element 209 and the third switch element 210, is applied to a liquid crystal cell 206.
The liquid crystal cell 206 maintains a display state based on the digital data signal, which has been stored in the digital memory element 250, until the first switch element 208 becomes conductive again and a new digital data signal is written into the digital memory element 250.
Further, at least one of the black display reference voltage and the white display reference voltage is an AC voltage whose polarity is reversed for each predetermined period. This prevents a decrease in reliability of the liquid crystal cell 206.